In prior semiconductor devices, there may be a double-gate switching element having two independent gate electrodes integrally. Patent Document 1 discloses a semiconductor device having a certain gate electrode and a remaining gate electrode. The semiconductor device may be configured to turn off the certain gate electrode after turning off the remaining gate electrode. In this structure, the remaining gate electrode may be turned off beforehand, to turn off the certain gate electrode after a part of carriers has been drawn out. Thus, a period of drawing out all carriers may decrease to increase turning-off speed.
A turning-off timing, at which the certain gate electrode is turned off afterwards, may be determined by setting a predetermined delay on a basis of a turning-off timing, at which the remaining gate electrode is turned off beforehand. In other words, a turning-on timing and the turning-off timing of the remaining gate electrode may be synchronized with a turning-on timing and a turning-off timing of an instruction signal, which controls a voltage applied to the gate electrodes. On the other hand, the certain gate electrode may need to be turned off after a predetermined period subsequent to the turning-off timing of the instruction signal.
In such a structure, a turning-on period of the certain gate electrode may be longer than a turning-on period regulated by the instruction signal. Thus, a duty ratio of the switching element as a whole may be longer than a duty ratio regulated by the instruction signal.
A turning-on timing of the certain gate electrode turned off afterwards may be delayed by the same time as a delay in the turning-off timing thereof. In such a structure, the turning-on timing and the turning-off timing of the switching element may be wholly delayed relative to the instruction signal.